eWeek Europe is reporting today that the UK Computational Cosmology Consortium (COSMOS) in Cambridge is one of SGI’s latest UV 1000 customers.

Stephen Hawking, who heads up that consortium, had this to say

“Recent progress towards a complete understanding of the universe has been impressive, but many puzzles remain,” said Hawking. “Cosmology is now a precise science, and we need supercomputers to calculate what our theories of the early universe predict and test them against observations of the present universe.”

Remember the UV 1000 is the big version of SGI’s Xeon-based shared memory machine. The UV will replace COSMOS’ current Altix 4700. According to SGI there is more to the buy than just hardware

Altix UV meets COSMOS’s requirements for high performance, scalable, big-memory supercomputing to facilitate vast amounts of data analysis. SGI is collaborating with COSMOS so that Altix UV, with its ease-of-use and rapid time-to-solution, begins contributing to research findings as quickly as possible. Collaboration efforts include: code porting to the Altix UV platform, applications knowledge transfers between SGI engineers and COSMOS users, parallel programmer support and end-user training. SGI engineers will also provide dedicated support to COSMOS researchers in strategic projects, following the Altix UV installation.

I’ve sent in for word on the size of the machine.

 

Related posts:

• Stephen Hawking narrates NCSA visualizations
• UK adds $20M to HPC pot for physics and astronomy computation
• SGI Announces Altix UV 1000 Customers

Found this at Dr. Dobb’s this morning

The Distributed European Infrastructure for Supercomputing Applications (DEISA) and the US National Science Foundation’s TeraGrid are jointly sponsoring HPC Challenges in Computational Sciences, October 4-7, in Acireale, Italy.

Applications are being accepted from graduate students and postdocs at US institutions through August 29. Awards will be announced by September 6. Successful applicants’ travel, lodging, and meals will be paid for by TeraGrid and DEISA.

 

Related posts:

• NSF supports attendance of over 100 students at upcoming TeraGrid conference
• TeraGrid conference call for papers
• TeraGrid Conference 2008

I’ve certainly written headlines that fell short of communicating the message as clearly as I’d have liked. It happens. But this one from Australia made me chuckle.

Remember when I reported on the new HP POD headed for iVEC in Australia? 107 TF, HP ProLiant, in a trailer.

The Sydney Morning Herald headline about that same story declares the following

Supercomputer to rival Google headed for Perth

They also report the system uses a “staggering” 9600 “central processing units” and cost $5M. I guess Google is running on Amigas connected with 1200 baud modems these days.

 

Related posts:

• Australia says world’s most powerful telescope will require world’s most powerful super
• HPC considered harmful…? [CORRECTED][UPDATED]
• Australia ups ante in race to host Square Kilometer Array with new supercomputing project

This series is about the men and women who are changing the way the HPC community develops, deploys, and operates the supercomputers we build on behalf of scientists and engineers around the world. John Shalf, this month’s HPC Rock Star, leads the Advanced Technology Group for Lawrence Berkeley National Lab, has authored more than 60 publications in the field of software frameworks and HPC technology, and has been recognized with three best papers and one R&D 100 award.

Among the works he has co-authored are the influential “View from Berkeley” (led by David Patterson, and others), the DOE Exascale Steering Committee, and the DARPA IPTO Extreme Scale Software Challenges report that sets DARPA’s information technology research investment strategy for the next decade.

He also leads the LBNL/NERSC Green Flash project — which is developing a novel HPC system design (hardware and software) for kilometer-scale global climate modeling that is hundreds of times more energy efficient than conventional approaches — and participates in a large number of other activities that range from the DOE Exascale Steering Committee to Program Committee Chair for SC2010 Disruptive Technologies exhibit.

Shalf’s energy and dedication to HPC are helping to actively shape the future of HPC, and that’s what makes him this month’s HPC Rock Star.

insideHPC: How did you get started in HPC?

John Shalf: I spent a lot of time as a kid hanging out in the physics department and computing center at Randolph Macon College (RMC) in Ashland, where I grew up.  The professors there gave me (and other neighborhood kids) accounts on their IBM mainframe and Perkin-Elmer unix minicomputer, and access to the supply rooms behind the classrooms were there were hundreds of computing technology artifacts such as 3D stacked core memories from old IBM systems, and adders constructed using vacuum tube logic.   My friends and I spent a lot of time in the summers and after school in 4th thru 6th grade, exploring the back rooms and having the professors patiently explain what we were looking at and how it worked.  We also got our first taste of the UNIX operating system and CRT terminals, albeit we learned more about playing Venture (a text video game) than programming.

When I was about 11, Dr. Maddry offered to teach me how to build a computer in exchange for my help cleaning up his lab during the summer.  We actually had a race where he built a computer using a Z80 chip, and I built my computer using an 8080a.  Both of our computers had 128 bytes (yes bytes… not kilobytes) of memory, ran at 500khz (could run faster if you turned off the fluorescent lights In the room), and was programmed using a set of dip-switches on the board.  I still remember the 8212 tristate latches and the TTL discrete logic chips we needed to glue everything together. I had a blast building it, and just as much fun programming it, despite the rudimentary nature of the user interface, and the low-resolution of the display system (12 LED’s lined up in a row to show the data and the memory addresses).  After that, I become hooked on computer architecture and machine design.

In college, I took my first HPC course and become interested in parallel computation. Where we got accounts on the HPC systems (Cray vector and IBM) at the NSF supercomputing systems. I was particularly fascinated with Thinking Machines systems, but also learned a lot about dataflow computing. Around this time, I collected many old machines through surplus auctions as well to learn how they worked. I had quite a collection of PDP-8s and PDP-11s, and started the Society for the Preservation of Archaic Machines (SPAM). The chemistry department maintained many PDP’s for their experiments, so they became a resource for manuals, circuit diagrams, advice on machine repair, and a FORTH interpreter that ran on top of RSTS.

During this time, I also discovered Ron Kriz’s vislab, where I developed an interest in computer graphics and visualization as another way to interact with the HPC community.  Whereas I had been connected to computing only through my study of computer architecture and programming, the vislab and working on programming / optimization of material science codes for the Engineering Science and Mechanics (ESM) department opened me up to direct collaboration with science groups.  It was there that I learned that the interdisciplinary collaborations in HPC is where the rubber hits the road.  That the pursuit of answers to scientific grand-challenges required such broad-based collaborations is what makes “supercomputing” so exciting.

insideHPC: What would you call out as one or two of the high points of your career — some of the things of which you are most proud?

Shalf: My first real job in HPC was at NCSA, where I divided my time between NCSA’s HPC consulting group  (led by John Towns), Ed Seidel’s General Relativity Group, and Mike Norman’s Laboratory for Computational Astrophysics.  This was the golden years for NCSA and the NSF HPC Centers program as well.  NCSA Mosaic was just getting popular. I got to work on HPC codes on a variety of platforms.  The LCA was developing its first AMR codes (Enzo).  I got to learn how to work on virtual reality programs in the CAVE, and participated in national-scale high-performance networking test beds for the SC1995 IWAY experiment.  There was such a wide variety of computer architectures — Cray YMP, a Convex C3880, and a Thinking Machines CM5.
What an amazing time!

It was also a time of great transition because it was clear that our vector machines were going to be turned off eventually and replaced by clusters of SMPs (SGI’s and Convex Exemplars initially, followed by clusters).  It’s very similar to what is happening to the HPC community today as we transition to multicore.  It was an exciting time to start in HPC. There were new languages like HPF, messaging libraries like PVM and P4, and MPI. It was unclear what path to take to re-develop codes for these emerging platforms, so we tried all of the options using toy codes.  Everyone was busily creating practice codes to try out each of these emerging alternatives to re-develop their entire code base to survive this massive transition of the hardware/software ecosystem.

The first few implementations of the parallel codes worked, but revealed serious impediments to future/collaborative code development.  When Ed Seidel’s group moved to the Max Planck Institute in Potsdam Germany, Paul Walker and Juan Masso hatched a plan to create a new code infrastructure, called Cactus, to combine what we’d learned about how to parallelize the application efficiently and hide the MPI code from the application developers with clever software engineering to support collaborative/multidisciplinary code development. Cactus was so titled by Paul because it was to “solve thorny problems in General Relativity”.  I had a huge amount of fun developing components for the first versions of Cactus, which is still used today (www.cactuscode.org).  We had a huge sense of purpose and dedication to the development of Cactus infrastructure — creating advanced I/O methods, solver plug-ins, remote steering/visualization interfaces, etc. I continued to work with subsequent Cactus developers (Gabrielle Allen, Tom Goodale, Erik Schnetter, and many others) many years after leaving Max Planck to extend it for Grid computing and new computing systems. One of the first things the group did when I came to LBNL was to run the “Big Splash” calculation on the NERSC “Seaborg” system, of inspiraling colliding black holes. The calculation was ground-breaking, in that it disproved a long-held model for initial conditions for these inspiraling mergers, and its demonstration of what you could do with large scale computing resources ultimately spawned the DOE “INCITE” program.  The work with the Cactus team is one of the highlights of my career, even though there was a cast of hundreds contributing to its success.

The Green Flash project is also one of the projects that has been a lot of fun. Like Cactus, there are a large number of people working on different aspects of this multi-faceted project. I definitely love this kind of broad interdisciplinary work. We get to re-imagine computing architecture, programming models, and application design massively parallel chip architectures that we anticipate will be the norm by 2018. Our multi-disciplinary team is on the forefront of applying co-design processes to the development of efficient computing systems for the future. There are a lot of similarities between the move towards manycore/power-constrained architectures and the massive disruptions that occurred at the start of my career when everyone was moving from vectors to MPPs. It is exciting to have such an open slate for exploration, and a time for radical concepts in computer architecture to be reconsidered.

insideHPC: What do you see as the single biggest challenge we face (the HPC community) over the next 5-10 years?

Shalf: The move to exascale computing is the most daunting challenge that the community faces over the next decade.  If we do not come up with novel solutions, then we will have to contend with a future where we must maintain our pace of scientific discovery without future improvements in computing capability.

The exascale program is not just about “exaFLOPS,” it’s about the phase transition of our entire computing industry that affects everything from cell phones to supercomputers.  This is as big a deal as the conversion from vectors to MPI two decades ago.  We cannot lose sight of the global nature of this disruption — that is not just about HPC.  DARPA’s UHPC program strikes the right tone here.  We need that next 1000x improvement for devices of all scales.  Until recently we have been limited by costs and chip lithography (how many transistors we could cram onto a chip), but now hardware is constrained by power, software is constrained by programmability, and science is squeezed in between.  Even if we solve those daunting challenges, science may yet be limited by our ability to assimilate results and even validate those results.

I think there is a huge problem with us conflating success in “exascale” with the idea that the best science must consume an entire exascale computing system (the same is true to some extent with our obsession with scale for “petascale.”). The best science comes in all shapes and sizes.  The investment profile should be more balanced towards scientific impact (scientific merit, whether it is measured in papers or US competitiveness).  There is a role for stunts to pave the way to understand how to navigate the path to the next several orders of magnitude of scaling.  But the focus should definitely be more on creating a better computing environment for everyone — more programmable, better performing, and more robust.

We do have a tendency to say that the solution to all of our programmability problems is just finding the right programming model.  This puts too much burden on language designers and underplays the role of basic software engineering for creating effective software development environments.  Dan Reed once said that our current software practices are “pre-industrial,” where new HPC applications developers join the equivalent of a “guild” to learn how to program a particular kind of application.  Languages and hardware play a role (just as the steam engine played a role in the start of the industrial revolution), but software engineering and good code structures that clearly separate the roles of CS experts from domain scientists (frameworks like Cactus, Chombo, and Vorpal) and algorithm designers are also critical areas that often get under-appreciated in the development of future apps.

insideHPC: How do you keep up with what’s going on in the community and what do you use as your own “HPC Crystal Ball?”

Shalf: For hardware design and computer science, attending many meetings to interact with the community plays an essential role in gauging the zeitgeist of the community.  Given the huge amount of conflicting information, you need to talk to a lot of people to get a more statistical view of what technology paths are actually practical and what is just wishful thinking.  Getting someone to talk over a beer is always more insightful for the “HPC Crystal Ball” than simply accepting their PowerPoint presentation or paper at face value.  You have to constantly look at what other people are doing.

I’ve always enjoyed the SIAM PP (SIAM Conference on Parallel Processing for Scientific Computing) and SIAM CSE (SIAM Conference on Computational Science and Engineering) meetings as a great source for seeing ideas that are still “in progress.”  Normally, conferences have a strict vetting process for papers.  The presented work is usually thoroughly vetted and mostly complete.  There is little opportunity to drastically change the direction of such work.  However, the SIAM meetings support having people getting together through mini-symposiums to discuss work that is still in progress, and in some cases, is not fully baked.  This is where there is a real exchange of wild ideas and new ways of thinking about solving problems.  I think there is a role for both types of meetings, but I definitely see more of the pulse of the community in the SIAM mini-symposiums.

I also find that journals that are targeted more at domain scientists have a lot of information about future directions of the community. You quickly find out what is important and why.  More importantly, you learn the vocabulary to actually communicate with scientists about their work.

insideHPC: What motivates you in your professional career?

Shalf: Scientists like to do things because they are interesting.  Engineers like to do things that are “useful”.  I’m an engineer who likes to hang out with scientists to get a bit of both the “interesting” and the “useful.”  If I can do things that are both interesting AND useful, I’m very happy.

There is a recent article in Science Magazine (Vol 329, July 16, 2010) entitled “learning pays off.” It showed research that people who went into science because they were excited by the science, and not simply because they were good at math, were the most likely to continue in the field.  This makes total sense to me.  I’m just a science geek.  I’m not a scientist or physicist by training, but I love to read Science and Nature magazine from cover to cover whenever a new one arrives.  I just love to learn new things and explore.  Supercomputing is a veritable smorgasbord of ideas and different science groups.  The deeper I dive into my professional career, the more I learn and the more people I meet who have radically different perspectives on computing and in science.  It’s so much fun to learn something new every day.

It’s also fun trying to be the man-in-the-middle to communicate between people with disparate backgrounds.  Because of my diverse interests, my career has run the gamut from Electrical Engineering and computer hardware design, to code development for a scientific applications team, to computer science, and then back again to hardware design.  I remember the perspective I had when I was in each of those different roles (when in EE, I thought the scientists were all just bad programmers, and when working for the apps group, I thought the hardware architects were just idiots who would not listen to the needs of the application developers).  All of the interesting things happening in supercomputing are happening in the communication between these fields, and I love to be there, right in the middle.  This is why co-design has become such a popular term: it’s where all of the action is today.

insideHPC: Are there any people who have been an influence on you during your years in this community?

Shalf: Many, many people.  Nick Liberante, and English professor with uncompromising standards for excellence, taught me how to organize thoughts for writing, and the importance of memorization to facilitate that organization process. Ron Kriz taught me the value of persistence, collaboration across multiple disciplines, and to be undaunted by the challenges of new and rapidly evolving technologies. Ed Seidel has had a huge influence on my career by launching me into the HPC business and teaching me how far you can push yourself if you set seemingly unrealistic stretch goals. Ed and Larry Smarr, Maxine Brown, and Tom Defanti demonstrated the power of demonstrating the “seemingly impossible” is within our grasp through ambitious demonstrations like the SC95 IWAY. Donna Cox taught me the magic that can result from bringing both scientists and artists together (seemingly disparate groups) to create powerful communication media. Tom Defanti taught me the importance of articulating what I want to do (either by writing, or presenting to others) by saying “It’s not a waste of time if you have the right attitude. You are writing the future.”  He also showed me how we can reinvent ourselves to take on new challenges as he went from CAVE VR display environments and jumped in to high performance international optical networking.

insideHPC: What type of ‘volunteer’ activities are you involved in — both professional activities within the community, and personal volunteer activities.

Shalf: I would say I’ve gotten way over committed to SC-related volunteer activities.  In the past, I’ve spent some time helping with the LBL summer high-school students program.  This year, I’ve gotten completely immersed in participating in the program committees and organization of HPC-related conferences.  I’m on the program committees for IPDPS, ISC, ICS, and SC.  It’s fun to participate in the organization and planning of so many different conferences, but it’s a lot of work.  I would like to get back to working with the high school and undergraduate students to get them excited about this field.

insideHPC: How can we both attract the next generation of HPC professionals into the community, and provide them with the experience-based training that they will need to be successful.

Shalf: Well, first we should call it “supercomputing” rather than HPC if we want to attract new talent.  It sounds interesting when a high-school kid says they want to work on supercomputers.  If they say they want to work on High Performance Computing, they’ll have their underwear pulled up around their ears by the class bully in no time.

I ended up in this field because of the patience of a few physics professors at RMC when I was growing up.  There is no degree in supercomputing (or HPC) because the field is fundamentally interdisciplinary.  So you have to catch kids early to get them excited about the breadth of experiences that supercomputing can offer.

Closing Comments from John Shalf

We are back in a transition phase for our entire hardware/software ecosystem that is much like the transition we made to MPI.  Times of disruption are also great times of opportunity for getting new ideas put into practice. The world is wide open with possibilities. It’s a great time to be involved in computing research.

 

Related posts:

• John Shalf Talks Programming Languages
• Q&A with John Shalf, chair of the Disruptive Technology showcase at SC10
• Rock Stars of HPC: Ricky Kendall

One the coolest file systems in User Space has got to be GlusterFS. It has a very unique architecture that allows it to be configured for specific storage requirements and scenarios. It can be used as a high-performance parallel file system, or a cloud based file system, or even a simple NFS server. All of this in user-space. Could GlusterFS represent the future of file system development for Linux?

This week the HPC Advisory Council announced a new university award program design to stimulate the dissemination of HPC research results.

“HPC is critically important to our economy and future, and its role is growing both in research and industry,” said Gilad Shainer, chairman of the HPC Advisory Council. “The University Award program is part of our ongoing effort to encourage and provide incentives for HPC education and advancement. We look forward to reviewing proposals, and working with the winners to highlight their research and further advances in HPC technology and education.”

“This is an excellent opportunity for students around the world to bring their research to life and highlight the end results to the HPC community,” said Hussein Nasser El-Harake at the Swiss National Supercomputing Centre who serves as the Director of the HPC Advisory Council Center of Excellence in Switzerland. “As part of the HPC Advisory Council’s award submission review team, we look forward to reviewing what students have planned for utilizing the performance power of clusters to solve interesting and important problems.”

Proposals are due by Oct 30, 2010, and can be submitted from the Council’s website. Winning submissions will receive a grant of time on the Council’s computing resources, travel expenses to present at one of the Council workshops, and publication of results on the Council website.

 

Related posts:

• HPC Advisory Council announces European workshop
• The HPC Advisory Council: bringing together users and providers in HPC
• Russian HPC maker T-Platforms joins HPC Advisory Council

Leveraging built-in Android Apps to make your app better

We already mentioned the award that the NVIDIA team received as part of DARPA’s UHPC program, but in fact four TA1 design teams were awarded funding as part of the program this week. DARPA released its own press release [PDF] which doesn’t say much new other than who is leading the winning teams: the four TA1 teams are Intel, NVIDIA, MIT’s CSAIL, Sandia; and the TA2 benchmark team is led by the Georgia Institute of Technology. We know that Cray is on NVIDIA’s team from the NVIDIA announcement. The only other vendor I’ve heard of that is playing a major role on one of the teams is SGI. According the grapevine SGI is on Intel’s team, but this has not been confirmed.

Timothy Prickett Morgan at The Register has little more in his coverage of the announcement, but so far the folks involved with the program aren’t saying much more than the very basics, and his article has quite a bit of speculation and rumor in it; in fact, we don’t even seem to know the total funding for the project so far, other than we know that NVIDIA got $25M over four years from their press release.

 

Related posts:

• NVIDIA-Led Team Scores a Spot on DARPA UHPC
• NVIDIA Professor Partnership awardees
• NVIDIA Launches Search for Next Great GPU Research Projects

The San Diego Supercomputer Center today announced that it will host a special conference in late October this year as it readies itself to deploy Gordon, their upcoming data intensive computing platform.  The conference, called “Grand Challenges in Data-Intensive Discovery”, will be held October 26-28 at SDSC.

Science has entered a data-intensive era, driven by a deluge of data being generated by digitally based instruments, sensor networks, and simulation devices,” said Michael Norman, interim director of SDSC. “Hence, a growing part of the scientific enterprise is associated with analyzing such data, placing special demands on computer architectures because the associated calculations have frequent I/O accesses, large memory requirements, and often limited parallelism.

Speakers and their respective topics include:

• Visual Arts – Lev Manovich, UC San Diego
  
• Needs and Opportunities in Observational Astronomy – Alex Szalay, Johns Hopkins University
  
• Transient Sky Surveys – Peter Nugent, Lawrence Berkeley National Laboratory
• Large Data-Intensive Graph Problems – John Gilbert, UC Santa Barbara
• Algorithms for Massive Data Sets – Michael Mahoney, Stanford University
• Needs and Opportunities in Seismic Modeling and Earthquake Preparedness Tom Jordan, University of Southern California
  
• Economics and Econometrics – James Hamilton, UC San Diego
  
• Needs and Opportunities in Fluid Dynamics Modeling and Flow Field Data Analysis – Parviz Moin, Stanford University
• …and many more

For more info, read their full release here.

 

Related posts:

• SDSC Dedicates New Building
• SDSC gets $20M from NSF for new flash-based super
• SDSC experimenting midrange flash-based supercomputer

Bright Computing announced today that Koi Computers has signed a reseller agreement for the the Bright Cluster Manager cluster management suite.  Bright Computing and Koi will also participate in joint marketing activities.

Koi Computers is very excited about this partnership because we believe the Bright Computing Manager. is a very comprehensive solution. The functionalities of the solution simplify the management and monitoring of thousands of nodes and complex clusters. I believe our clients will find this solution complete with everything they need to maximize their productivity,” said Fanny Ho, President of Koi Computers, Inc.

For more on the partnership, read their release here.

 

Related posts:

• Bright Computing And SICORP Sign Reseller Agreement
• Bright Computing and Eurotech Sign Reseller Agreement
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Verari has announced that they have changed the sign on the front of the building.  Why, you ask?  They’re focusing their business model specifically on providing hardware for cloud-like environments.  You mean big datacenters?  Yeah, those too.

Being able to base our cloud storage and compute products on Verari’s world class BladeRack® 2 Series technology and FOREST containerized data center infrastructure puts us at the front of the pack to serve the demanding cloud customer,” said Marc Brown, President and COO, Cirrascale. “These products, based on Verari’s patented Vertical Cooling Technology, generated over $500 Million in installed systems in the high performance computing and enterprise markets; these customer segments are the foundation of the burgeoning cloud market of today. This technology is a winning formula for the cloud customer.”

Cirrascale was actually organized under the “Verari Technologies” name while acquiring the intellectual property and other assets of Verari Systems back in January 2010.

Technology innovation is only half the story at Cirrascale; we must also innovate with our business model,” said Dave Driggers, Chairman and CEO, Cirrascale. “Cloud and Web 2.0 businesses are placing new demands on their suppliers. Unlike the enterprise data center customer served by traditional computer companies with established product lines and large IT consulting businesses, the agile, self-sufficient cloud and web 2.0 customers want to collaborate to define their platforms and create a purpose-built data center infrastructure that addresses their unique requirements.”

Quoting their release: “Cirrascale will focus on customers buying at the data center and rack infrastructure level, across a range of storage and computing models including low-power micro-servers, high density storage, scale-out multi-core, HPC cluster and GP/GPU computing. Customers are served by the same physical rack infrastructure that accommodates the customer-defined power, density and cooling requirements.”  This sounds surprisingly like the previous Verari business model. It also sounds very much like the business model of Rackable, now SGI and portions of the Dell business.  Ultimately, this is a very tough market niche.

For more info, read their full press release here.

 

Related posts:

• SGI announces it is first in line at the Verari buffet
• Verari Hits Milestone Blade Shipment
• Verari lands $20M in financing

Governor Deval Patrick joined by UMass President Jack Wilson and Holyoke Mayor Elaine Pluta, today announced that the Holyoke High Performance Computing Center at the Mastex site.  Huh?  The eventual site of the new Massachusetts supercomputing center is located between Cabot and Appleton Streets in the downtown canal district.

We are on track to deliver new jobs and tech innovation to all of western Massachusetts,” said Governor Patrick. “This project will anchor a vibrant new growth district in the Pioneer Valley.”

Selecting this site is a major step forward for the development of the Holyoke High Performance Computing Center,” said Lieutenant Governor Timothy Murray. “This project, which will lead to downtown redevelopment and growth in the City of Holyoke, is another example of our administration strategically investing in jobs and innovation in all regions of the Commonwealth.”

The Patrick-Murray administration has pledged $25 million toward the construction of the new site.  This, combined with the contributions of university partners and the University Consortium bring the grand build total to $75 million.

The announcement of a final location for the Holyoke High Performance Computing Center brings us one significant step forward towards the economic development and jobs that this project will mean for Holyoke. I’m proud to stand with Governor Patrick as he makes this announcement, and am grateful that his Administration continues to invest in projects, such as this, that create jobs now and lay the foundation for a strong economy for years to come,” said Representative Michael Kane.

For more info on the new HPC digs in Holyoke, read the full article here.

 

Related posts:

• Massachusetts Governor Announces Initial Holyoke HPC Construction Plan
• Mass Governor Pledges $25 Million For Holyoke HPC
• HPC Confusion in Holyoke

Cloud and Multi-core offer new modes of High Performance Computing. Will it suit your needs?

ScaleMP announced news today that they were chosen by the University of Florida’s Interdisciplinary Center for Biotechnology Research [ICBR], a research center dedicated to providing biotechnology research services to the UF community.  The ICBR will use the vSMP technology alongside existing infrastructure in order to leverage both legacy and proprietary software packages.  They will also allow researchers to submit larger interactive jobs.

Many organizations have a sufficient amount of computational power and enough CPUs, but they are simply unable to leverage their existing infrastructure for larger compute intensive workloads,” said Shai Fultheim, founder and CEO of ScaleMP. “vSMP Foundation for SMP enables biotechnology organizations like ICBR to aggregate existing hardware and to create a virtual SMP for next generation sequence processing and other biotechnology computing needs that need large amounts of processing power as well as shared memory.”

ICBR’s IT team supports research at UF and abroad in various biotechnology fields such as proteomics, genomics, bioinformatics and cellomics. ICBR needed to be able to run legacy software as well as proprietary software packages requiring large shared memory systems. Because of the high price point of traditional SMP systems, the team tried to find other ways to perform these jobs. They ended up stretching their virtual infrastructure to accommodate these large shared memory workloads, resulting in a loss of virtualization benefits.

For more info on the University of Florida’s use of vSMP, check out the ScaleMP website here.

 

Related posts:

• ScaleMP Announces Record Breaking SPEC Results
• ScaleMP Delivers for Coventry University
• ScaleMP Announces vSMP for Cloud

Members of the Holyoke Innovation Design and Development Task Force have begun to speculate on the potential economical impacts of building the upcoming HPC center.  All things being equal, an HPC center of that size doesn’t require a vast army of support and operations staff.  The group, tasked with working with the Massachusetts Technology Collaborative, a quasi-public state economic development agency, to figure out exactly what the Pioneer Valley needs to do to properly harness the computing center, speculates that the site will require around 20 staff members for operations.  So where do the rest of the economic development prospects come from?

They will come here, in my estimation, if we give them a reason to,” said Timothy W. Brennan, executive director of the Pioneer Valley Planning Commission.

What if there were research tax credits for the innovation district of Holyoke?” Brennan said.

James F. Kurose, a distinguished professor of computer science and executive associate dean for the college of natural sciences at the University of Massachusetts at Amherst, hopes that the specialty computational capability found at the site will attract companies and research organizations seeking computational horsepower and research talent.

My personal hope is that downtown Holyoke can serve as a nexus, because of the talent pool, because of the high performance computing center,” Kurose said.

Unfortunately, weighing the potential economic benefits is very difficult.  Garnering research attention, many times, requires years of development and financial assistance.  Even then, the development activities and funding must be continually sought out in order to preserve those relationships.

For more info on this story, check out the source article here.

 

Related posts:

• Holyoke Computing Center Panel First Meeting
• Final Holyoke Site Announced
• Holyoke Computing Center Almost Official

NVIDIA was the first of four teams to announce that they have been awarded a slice of the DARPA Ubiquitous High Performance Computing [UHPC] program.  NVIDIA led a team that also included Cray, Oak Ridge National Lab and six top universities.  From the looks of it, they took a page from How to Be the Best at Everything and gathered a team of supercomputing juggernauts.  The four-year contract award includes $25 million in funding and a shot at the latter portions of the program [via down selection].

This recognizes NVIDIA’s substantial investments in the field of parallel processing and highlights GPU Computing’s position as one of the most promising paths to exascale computing,” said Bill Dally, NVIDIA’s chief scientist and senior vice president of research, and the team’s principal investigator. “We look forward to collaborating to develop programmable, scalable systems that operate in tight power budgets and deliver increases in performances that are many orders of magnitude above today’s systems.”

The DARPA UHPC program is attacking technical issues that are key to the future of high performance computing, from the embedded terascale to the exascale,” said Steve Scott, Cray’s senior vice president and CTO, and the Cray principal investigator on the team. “We are excited to be working with this team, and we believe the directions we are pursuing will lead to radical improvements to the state-of-the-art in the coming decade.”

The eventual platform developed by the team will crest the exascale mark proposed by the original DARPA agency announcement.  From the looks of the team, the universities will perform much of the up-front investigation, especially with respect to software.  NVIDIA will likely lead the charge in the core silicon department and Cray will probably handle the platform and RAS features.

For more info on NVIDIA’s participation, check out their news release here.  For more info on DARPA’s UHPC program, check out the program website here.

 

Related posts:

• The rest of the UHPC awardees, and not much else
• DARPA announces Omnipresent HPC program
• DARPA calls for petaflops-in-a-rack proposals

After months of silence, OpenSolaris supporters have had enough and launched the Illumos project. Described as a "spork" of OpenSolaris, rather than a true fork, Illumos is a misguided attempt to keep the Solaris legacy OS alive for another generation. Too bad it's doomed from the start.

c|net reported in an article last week that Bill Gates has called for better software for a range of problems, including nuclear software and disease modeling

“There’s no disease-modeling software,” he said, speaking at the end of the three-day Techonomy conference here. “There is none. Why is flu seasonal? We don’t know.”

Gates said he aims to make sure that gap is filled, supporting development of the tools needed to do such modeling, while he also wants to use modeling to further explore nuclear power options, such as the Terrapower effort he is backing. “On paper it’s quite amazing but it is hard to go from here to there,” he said.

Gates said he also plans to offer up the modeling software package for free for others to use.

Those of you at the intersection of computing and systems modeling might be interested in hitting up Gates for a couple Benjamins.

 

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• NIH grant helps TGen search genes for the causes of disease

This isn’t a review, but given the popularity of my last CUDA book review, I thought I’d mention that Addison-Wesley has published a new book called CUDA by Example: An Introduction to General-Purpose GPU Programming. The book is written by NVIDIA’s Jason Sanders and Edward Kandrot, both software engineers on the CUDA team.

From NVIDIA’s description of the book

CUDA by Example, written by two senior members of the CUDA software platform team, shows programmers how to employ this new technology. The authors introduce each area of CUDA development through working examples. After a concise introduction to the CUDA platform and architecture, as well as a quick-start guide to CUDA C, the book details the techniques and trade-offs associated with each key CUDA feature. You’ll discover when to use each CUDA C extension and how to write CUDA software that delivers truly outstanding performance.

Table of Contents

• Why CUDA? Why Now?
• Getting Started
• Introduction to CUDA C
• Parallel Programming in CUDA C
• Thread Cooperation
• Constant Memory and Events
• Texture Memory
• Graphics Interoperability
• Atomics
• Streams
• CUDA C on Multiple GPUs
• The Final Countdown

Here’s a link to the book at Amazon (non-affiliate link).

 

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Intel has started talking about about Knights Ferry, the manycore development platform that precedes the Knights Corner chip. Both are part of the Many Integrated Core (MIC) architecture announced in May; Knights Ferry was briefed by Kirk Skaugen ISC’10.

PGI’s Michael Wolfe wrote an interesting overview of Knights Ferry for HPCwire late last week that compares the chip to Fermi and discussed the similarities to Larrabee, the little platform that couldn’t.

The Knights Ferry has 32 x86 cores on chip, each with 32KB L1 instruction cache, 32KB L1 data cache, and 256KB L2 cache. I will refer to them as 32 processors. Each processor has a vector unit, essentially a very wide (512 bits or 16 floats) SSE unit, allowing 16 single precision floating point operations in a single instruction. Double-precision compute throughput is half that of single-precision. The 32 data caches are kept coherent by a ring network, which is also the connection to the on-chip memory interface(s). Each processor supports a multithreading depth of four, enough to keep the processor busy while filling an L1 cache miss. The Knights Ferry is implemented on a PCI card, and has its own memory, connected to the host memory through PCI DMA operations. This interface may change in future editions, but Intel advertises the MIC as “an Intel Co-Processor Architecture.” This could be taken as acknowledgement that accelerators can play a legitimate role in the high performance market.

 

Related posts:

• Intel Details Future Graphics Silicon
• Intel Mumbles Details on Supercomputing Project
• Details on Intel’s 8 core chip